Senior Digital Verification Engineer
Synopsys
Pavia, ITALY
2 gg fa

and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence.

The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.

If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC faster. We offer the world’s broadest portfolio of silicon IP predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.

All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications.

And get differentiated products to market quickly with reduced risk.

Senior Digital Verification Engineer

Seeking a highly motivated and innovative digital verification engineer with exceptional knowledge in the verification of high-speed digital designs.

The candidate would be working as part of a highly experienced mixed-signal design and verification team, and be involved in verifying current and next generation NRZ and PAM-based SerDes products.

The position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers responsible for delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips.

Responsibilities of this job include

  • Writing modular constrained-random Verilog and SystemVerilog testbenches
  • Performing functional coverage
  • Assertion coverage and code coverage
  • Creating and tracking test-plans
  • Analyzing failure cases and running gate-level simulations
  • Key Qualifications

  • BSEE or MSEE with 5+ years of digital verification experience in the industry
  • Must have hands-on experience in writing complex testcases in Verilog and SystemVerilog
  • Must have familiarity with code quality metrics
  • Preferred Experience / Knowledge

  • High-speed digital & mixed-signal design & verification
  • Asynchronous clock domain crossing
  • Familiar with UVM methodology and verification using VCS / Verdi
  • Good organization and communication skills
  • Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

    Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process.

    Should you require an accommodation, please contact hr-help-canada synopsys.com.

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