FPGA Engineer – Aerospace & Defence
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RINA is looking for an FPGA Engineer Aerospace & Defence to expand our team in Rome. As an FPGA Engineer for the Aerospace & Defence Unit you will take care of the development and design of SDR (Software Defined Radio) and Radar - AESA (Active Electronically Scanned Array) systems.

Desired Skills and Experience : Electronic Engineering Degree At least 2 years experience of Knowledge of the FPGA devices of the Xilinx family, with particular propensity for Digital Signal Processing (tool System Generator) and adequate knowledge of the Xilinx IP catalog Knowledge of Xilinx System on Chip, (FPGA ZINQ) and competence in the design and development of firmware / software.

Experience with RTOS. Knowledge of FPGA devices of the Altera / Intel family, with particular propensity for Digital Signal Processing (DSP Builder tool) and adequate knowledge of the Altera / Intel IP catalog.

Knowledge of Altera / Intel System on Chip, (soft risk NIOS II) and competence in firmware design and development In addition, significant experiences with family DSP devices will be particularly appreciated : Analog Devices TIGER SHARC DSP DA VINCI DSP Texsas Instruments and an easy knowledge of : Matlab and Matlab-Simulink Standards DO254 / DO-178 Languages : VHDL / Verilog / AHDL language C / C ++ language Other Requirements : Team worker, yet also accustomed to working independently, on challenging and diversified activities Capable to work in a multi-disciplinary team dedicated to complex projects Problem solving attitude Result focused Adaptability and availability Applications that are not in line with the requirements will not be considered.

This job offer is extended to both sexes, in accordance with the Italian Law (Legislative Decree 198 / 2006 and subsequent amendments and additions).

Le candidature non in linea con i criteri di ricerca non saranno prese in considerazione. L'offerta di lavoro di lavoro si intende riferita ad entrambi i sessi in accordo con il D.

Lgs 198 / 2006 e s.s.m.i. #LI-MM1

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