Vimercate, MB, IT
4 gg fa
source : SuccessFactors

Req. ID : 153221


As an Emerging Memory Physical Design Engineer at Micron Technology, Inc. you will be responsible for the physical mask design of advanced analog and mixed-signal integrated circuits.

You will be required to meet all engineering and process criteria needed for various memory technologies. You will collaborate with other engineering groups to apply cutting edge layout techniques for the design and verification of digital and analog circuits.

You will be expected to understand various circuit design protocols, different fabrication processes, mask generation techniques, and tape-out processes and procedures.

Responsibilities and Tasks

Develop the Physical Design of Emerging Memory Testchips or Product Demonstrators

  • Develop floor plans optimized for circuit performance, die size and block positioning
  • Design custom layout of digital, analog and mixed signal circuits ranging from simple cells to large complex sections, including full chip construction
  • Apply layout techniques including matching, area optimization, pitch matched layout
  • Collaborate with Design Engineers to ensure optimal implementation of physical designs
  • Execute the Verification and Quality Flows Required by the Fabrication Process

  • Use verification tools to drive cells and blocks clean through all required flows for any given process. Typical required flows include Design Rule Checking (DRC), Layout versus Schematic (LVS) and Nodal Area Check (NAC)
  • Ensure layout meets Design for Manufacturability (DFM) requirements
  • Use extraction and analysis tools to identify and fix all electro migration and IR Drop issues prior to tape-in
  • Develop, maintain, and share technical knowledge


    Bachelors Degree or Diploma (High School Degree) required


    Experience in Layout Engineering is preferred but not required.

    Areas of experiences are following :

    Drawing memory with knowledge of hierarchical layout planning

  • Layout experience with submicron technologies
  • Fundamental understanding of Design For Manufacturability (DFM) layout techniques
  • Familiarity with Cadence Virtuoso (DFII, Opus) layout environment and UNIX.
  • Good understanding of custom analog and digital layout optimization
  • Able to understand EM / IR issues and fix layout accordingly
  • Ability to accurately plan and schedule responsibilities
  • Experience in hierarchical verification physical verification checks at block level and section level.
  • Strong verbal and written communication skills.

  • Work independently and collaborate within a worldwide team.
  • Thrive in a dynamic and fast-paced work environment.
  • All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

    For US Sites Only : To request assistance with the application process and / or for reasonable accommodations, please contact Micron’s Human Resources Department at 1-800-336-8918

    or 208-368-4748

    and / or by completing our General Contact Form

    Keywords : Vimercate Monza e Brianza (IT-MB) Italy (IT) Technology Development Experienced Regular Engineering Not Applicable Tier 3

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